1. Field of the Invention
Example embodiments relate to an image sensing technology, and more particularly, to a CMOS image sensor having an up/down ripple counter which may prevent the change of data during a count operation. Example embodiments also relate to a method of operating a CMOS image sensor. Also, example embodiments relate to a CMOS image sensor which may allow a reduction in size of an analog-to-digital conversion circuit included in a CMOS image sensor and increase operation speed of the CMOS image sensor.
2. Description of Related Art
Image sensors of semiconductor devices generally convert an optical image to an electric signal. A charge coupled device (CCD) using coupling of charges and a CMOS image sensor (CIS) are widely used as image sensors. In general, the CIS is widely used in a variety of fields because generally a low voltage operation is possible and less power is consumed compared to the CCD. Also, the CIS using a standard CMOS process is considered by some to be advantageous for integration and may replace the CCD in many fields in the future.
The CIS requires an operation of converting an analog signal output from an active pixel sensor (APS) array to a digital signal, unlike the CCD. Thus, for the conversion, the CIS uses an analog-to-digital converter (ADC).
For example, a CIS may include a single ADC type and/or a column ADC type according to a conventional analog-to-digital conversion method. The single ADC type is to convert analog pixel signals output from all columns to digital signals within a desired and/or predetermined time period by using a single ADC that operates at high speed. The single ADC may have the merit of reducing the size of a chip where the ADC is embodied. However, since the single ADC is generally operated at high speed, power consumption is generally high.
In a column ADC type, an ADC having a simple structure is arranged for each column. Accordingly, the power consumption is generally smaller than that of the single ADC type. However, the size of a chip where the ADC is embodied increases as the number of columns of the APS array increases.
FIG. 1 is a block diagram schematically illustrating a conventional CMOS image sensor. Referring to FIG. 1, a CMOS image sensor 1 includes a timing controller 3, a row driver 5, an APS array 7, a reference voltage generator 9, and a plurality of ADCs 11-1, 11-2, 11-3, . . . , 11-n, where “n” is a natural number. Control logic generates a plurality of control signals (DIR, CLK, TX1, and TX2).
Each of the ADCs includes a comparator, an up/down ripple counter and a memory device. Referring to FIG. 1, ADC 11-1 includes comparator 13-1, up/down ripple counter 15-1 and memory device 17-1; ADC 11-2 includes comparator 13-2, up/down ripple counter 15-2 and memory device 17-2; ADC 11-3 includes comparator 13-3, up/down ripple counter 15-3 and memory device 17-3; . . . ; and ADC 11-n includes comparator 13-n, up/down ripple counter 15-n and memory device 17-n. 
Each of the comparators 13-1, 13-2, 13-3, . . . , 13-n receives and compares a pixel signal output through each column of the APS array 7 and a ramp signal Vramp output from the reference voltage generator 9 and outputs a result of the comparison.
Each of the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n counts a state transition time of a comparison signal output from each of the comparators 13-1, 13-2, 13-3, . . . , 13-n based on a clock signal CLK. Each of the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n operates as either an up-counter or a down-counter. Whether the up/down ripple counter operates as an up-counter or a down counter may be determined based on a direction signal DIR, which may be output from the control logic. In the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n, a problem is that output values (e.g., count values) of the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n change at the moment when a count operation is switched to a stop operation or vice versa.
The memory devices 17-1, 17-2, 17-3, . . . , 17-n receive and store the count value output from the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n, respectively. The memory devices 17-1, 17-2, 17-3, . . . , 17-n may receive and store the count values in response to a first transmission control signal TX1 provided by the control logic and may output the stored count values through a sensor amplifier 19 via data bus DBUS in response to a second transmission control signal TX2 provided by the control logic.
Each of the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n and each of the memory devices 17-1, 17-2, 17-3, . . . , 17-n is embodied by a plurality of flip-flops. For example, each of the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n and each of the memory devices 17-1, 17-2, 17-3, . . . , 17-n include as many flip-flops as the number of data bits for converting pixel signals to digital signals. Also, as the resolution of the APS array 7 increases, the number of columns of the APS array 7 increases. Thus, the size of an area occupied by the ADCs increases as the APS array 7 increases. Similarly, the size of an area occupied by the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n and the memory devices 17-1, 17-2, 17-3, . . . , 17-n is increased as the APS array 7 increases.
Still referring to FIG. 1, the memory devices 17-1, 17-2, 17-3, . . . , 17-n respectively output the count value output from the up/down ripple counters 15-1, 15-2, 15-3, . . . , 15-n to the sensor amplifier 19 via the DBUS. The sensor amplifier 19 detects and amplifies a received count value and outputs a result of the amplification.
As shown in FIG. 1, each of the memory devices 17-1, 17-2, 17-3, . . . , 17-n respectively included in the ADCs 11-1, 11-2, 11-3, . . . , 11-n outputs a count value using the DBUS. In view of the sensor amplifier 19, the DBUS receives a considerably large load. The transmission speed of the count value output from each of the memory devices 17-1, 17-2, 17-3, . . . , 17-n decreases as the load increases. Therefore, a method to increase the speed of the data transmitted from each of the memory devices 17-1, 17-2, 17-3, . . . , 17-n to the sensor amplifier 19 is needed.